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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>F:\TangPrimer-25K-example\pmod_lcd\src\top.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-3</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Aug 24 18:08:04 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>lcd114_test</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.35s, Peak memory usage = 317.883MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 317.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 317.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 317.883MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 317.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 317.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 317.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 317.883MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 317.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 317.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 317.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 317.883MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 317.883MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 317.883MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 317.883MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>9</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>5</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTBUF</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>74</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>10</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>64</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>289</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>27</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>52</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>210</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>21</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>21</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>310(289 LUT, 21 ALU) / 23040</td>
<td>2%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>74 / 23280</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 23280</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>74 / 23280</td>
<td><1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 56</td>
<td>0%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>clk_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>100.0(MHz)</td>
<td>212.3(MHz)</td>
<td>7</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.290</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.511</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.801</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_3_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>cmd_index_0_s1/CLK</td>
</tr>
<tr>
<td>1.230</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>50</td>
<td>cmd_index_0_s1/Q</td>
</tr>
<tr>
<td>1.410</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1106_s244/I0</td>
</tr>
<tr>
<td>1.915</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>n1106_s244/F</td>
</tr>
<tr>
<td>2.095</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1458_s32/I0</td>
</tr>
<tr>
<td>2.600</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1458_s32/F</td>
</tr>
<tr>
<td>2.780</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1458_s25/I0</td>
</tr>
<tr>
<td>3.285</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1458_s25/F</td>
</tr>
<tr>
<td>3.465</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1458_s18/I1</td>
</tr>
<tr>
<td>3.961</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1458_s18/F</td>
</tr>
<tr>
<td>4.141</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1458_s14/I0</td>
</tr>
<tr>
<td>4.646</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1458_s14/F</td>
</tr>
<tr>
<td>4.826</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1458_s13/I0</td>
</tr>
<tr>
<td>5.331</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1458_s13/F</td>
</tr>
<tr>
<td>5.511</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_data_3_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_data_3_s2/CLK</td>
</tr>
<tr>
<td>10.801</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spi_data_3_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.022, 64.997%; route: 1.260, 27.104%; tC2Q: 0.367, 7.899%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.439</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.801</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>cmd_index_0_s1/CLK</td>
</tr>
<tr>
<td>1.230</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>50</td>
<td>cmd_index_0_s1/Q</td>
</tr>
<tr>
<td>1.410</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1106_s244/I0</td>
</tr>
<tr>
<td>1.915</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>n1106_s244/F</td>
</tr>
<tr>
<td>2.095</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1464_s40/I2</td>
</tr>
<tr>
<td>2.538</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1464_s40/F</td>
</tr>
<tr>
<td>2.718</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1464_s35/I1</td>
</tr>
<tr>
<td>3.213</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1464_s35/F</td>
</tr>
<tr>
<td>3.393</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1464_s29/I1</td>
</tr>
<tr>
<td>3.889</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1464_s29/F</td>
</tr>
<tr>
<td>4.069</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1464_s27/I0</td>
</tr>
<tr>
<td>4.574</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1464_s27/F</td>
</tr>
<tr>
<td>4.754</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1464_s26/I0</td>
</tr>
<tr>
<td>5.259</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1464_s26/F</td>
</tr>
<tr>
<td>5.439</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_data_0_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_data_0_s2/CLK</td>
</tr>
<tr>
<td>10.801</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spi_data_0_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.950, 64.447%; route: 1.260, 27.530%; tC2Q: 0.367, 8.023%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.415</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.386</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.801</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_1_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>cmd_index_0_s1/CLK</td>
</tr>
<tr>
<td>1.230</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>50</td>
<td>cmd_index_0_s1/Q</td>
</tr>
<tr>
<td>1.410</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1107_s247/I0</td>
</tr>
<tr>
<td>1.915</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>n1107_s247/F</td>
</tr>
<tr>
<td>2.095</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1462_s24/I0</td>
</tr>
<tr>
<td>2.600</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1462_s24/F</td>
</tr>
<tr>
<td>2.780</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1462_s21/I2</td>
</tr>
<tr>
<td>3.223</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1462_s21/F</td>
</tr>
<tr>
<td>3.403</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1462_s19/I1</td>
</tr>
<tr>
<td>3.899</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1462_s19/F</td>
</tr>
<tr>
<td>4.079</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1462_s16/I0</td>
</tr>
<tr>
<td>4.584</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1462_s16/F</td>
</tr>
<tr>
<td>4.764</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1462_s13/I2</td>
</tr>
<tr>
<td>5.207</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1462_s13/F</td>
</tr>
<tr>
<td>5.386</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_data_1_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_data_1_s2/CLK</td>
</tr>
<tr>
<td>10.801</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spi_data_1_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.897, 64.032%; route: 1.260, 27.851%; tC2Q: 0.367, 8.117%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.424</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.377</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.801</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_5_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>cmd_index_0_s1/CLK</td>
</tr>
<tr>
<td>1.230</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>50</td>
<td>cmd_index_0_s1/Q</td>
</tr>
<tr>
<td>1.410</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1107_s247/I0</td>
</tr>
<tr>
<td>1.915</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>n1107_s247/F</td>
</tr>
<tr>
<td>2.095</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1454_s27/I0</td>
</tr>
<tr>
<td>2.600</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1454_s27/F</td>
</tr>
<tr>
<td>2.780</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1454_s24/I2</td>
</tr>
<tr>
<td>3.223</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1454_s24/F</td>
</tr>
<tr>
<td>3.403</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1454_s19/I1</td>
</tr>
<tr>
<td>3.899</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1454_s19/F</td>
</tr>
<tr>
<td>4.079</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1454_s15/I1</td>
</tr>
<tr>
<td>4.574</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1454_s15/F</td>
</tr>
<tr>
<td>4.754</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1454_s13/I2</td>
</tr>
<tr>
<td>5.197</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1454_s13/F</td>
</tr>
<tr>
<td>5.377</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_data_5_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spi_data_5_s2/CLK</td>
</tr>
<tr>
<td>10.801</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spi_data_5_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.887, 63.955%; route: 1.260, 27.911%; tC2Q: 0.367, 8.134%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.553</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.248</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.801</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>lcd_dc_r_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>cmd_index_0_s1/CLK</td>
</tr>
<tr>
<td>1.230</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>50</td>
<td>cmd_index_0_s1/Q</td>
</tr>
<tr>
<td>1.410</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1106_s244/I0</td>
</tr>
<tr>
<td>1.915</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>n1106_s244/F</td>
</tr>
<tr>
<td>2.095</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1448_s22/I0</td>
</tr>
<tr>
<td>2.600</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1448_s22/F</td>
</tr>
<tr>
<td>2.780</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1448_s19/I0</td>
</tr>
<tr>
<td>3.285</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1448_s19/F</td>
</tr>
<tr>
<td>3.465</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1448_s16/I1</td>
</tr>
<tr>
<td>3.961</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1448_s16/F</td>
</tr>
<tr>
<td>4.141</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1448_s26/I3</td>
</tr>
<tr>
<td>4.393</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1448_s26/F</td>
</tr>
<tr>
<td>4.573</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n1448_s10/I1</td>
</tr>
<tr>
<td>5.069</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>n1448_s10/F</td>
</tr>
<tr>
<td>5.248</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>lcd_dc_r_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>lcd_dc_r_s2/CLK</td>
</tr>
<tr>
<td>10.801</td>
<td>-0.061</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>lcd_dc_r_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.759, 62.900%; route: 1.260, 28.728%; tC2Q: 0.367, 8.372%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
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